Moved to catiss repo.

Migrate the original code from OpenXiangShan and re-write it with C++
style classes for the upstream riscv-isa-sim.

Rocket-chip restricts the values of MSTATUS.FS.

rocket-chip sets the xtval to instruction values when exceptions.
However, XiangShan and NutShell simply clear it, which is also
compatible with the RISC-V ISA.

It seems sim_t::addr_to_mem allocates the memory of only PGSIZE bytes
at every time. Therefore, we need to separate memcpy operations.

Different DUTs may have different physical address bits.

Both rocket-chip and NutShell do not implement ASIDs.

We add diff_trace_t class to record Spike's actions including

* instructions executed
* store requests
* load requests
* page-table walker requests

With the above information, we add support for the store commit
diff.

Rocket-chip sets the value to zero.

Load operations may cause exceptions. The is_amo flag must be set
just before the store is processed.

This commit adds the Sdtrig ISA string for the RISC-V Triggers
extension with permission check for the related CSRs.

This CSR only exists if Sdtrig is enabled.

* misa
* satp
* mimpid
* marchid

Practical hardware designs would have reservation sets of 64B.
However, Spike seems to have only byte-level reservation sets.

I'm not sure whether it would violate the ISA.

If virtual memory has not been enabled, the CPU is not expected
to cache any PTEs and should not behave differently with Spike.

There was a macro MAX_INSN_LENGTH, but it seems not to be used anywhere.
We use it to decode the maximum insn_length.

When skipping instructions, minstret should be incremented.